The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasing interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain (S/D) junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain doping profiles become increasingly difficult to meet when conventional device structures, based on bulk silicon (Si) substrates, are employed. Innovations in front-end process technologies or the introduction of alternative device structures are required to sustain the historical pace of device scaling.
For device scaling well into the sub-30 nm regime, a promising approach to controlling short-channel effects is to use an alternative device structure with multiple-gate electrodes. Examples of multiple-gate structures include the double-gate structure, triple-gate structure, omega-FET structure, and the surround-gate or wrap-around gate structure. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
A simple example of a multiple-gate device is the double-gate MOSFET structure, where there are two gate electrodes on the opposing sides of the channel or silicon body. A one way to fabricate a double-gate MOSFET is described by U.S. Pat. No. 6,413,802B1, issued to Hu et al, for FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. In U.S. Pat. No. 6,413,802B1, the device channel comprises a thin silicon fin formed on an insulative substrate (e.g. silicon oxide) and defined by using an etchant mask. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate structure overlying the sides of the fin. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface. The specific device structure, the cross-section of which is illustrated in FIG. 1A, is widely recognized to be one of the most manufacturable double-gate structures. A plane view of the double-gate structure 10 is shown in FIG. 1B. The etchant mask 12 of U.S. Pat. No. 6,413,802B1 is retained on the fin 20 in the channel region through the process. The device width of a single fin is defined to be twice the fin height h. Multiple device widths may be achieved on the same substrate 14 by placing multiple fins 22,24 in parallel, as illustrated in device 30 in FIG. 2. An inverter circuit may be formed using N-channel and P-channel MOSFETs comprising such multiple fins. In another embodiment of U.S. Pat. No. 6,413,802B1, an inverter circuit 40 is implemented using N-channel and P-channel MOSFETs 42,44 that are vertically aligned and separated by a dielectric layer 46, as illustrated in FIG. 3.
Another example of the multiple-gate transistor is the triple-gate transistor 50. The cross-section of the triple-gate transistor structure 50 is illustrated in FIG. 4A. The plane view of the triple-gate structure 50 is shown in FIG. 4C. The triple-gate transistor structure 50 has three gates: one gate on the top surface 52 of the silicone body/fin, and two gates on the sidewalls 54,56 of the silicon body/fin. The triple-gate device achieves better gate control than the double-gate device because it has one more gate on the top surface 52 of the silicon fin.
While there is some work on the design and fabrication of multiple-gate devices such as the double-gate and triple-gate devices, there is little work on circuits, such as inverter circuits, configured using such devices. The relentless pursuit of high-performance has pushed logic and circuit designers to utilize every delay and area optimization technique at their disposal. However, the optimization of circuits, such as inverter circuits, incorporating multiple-gate transistors has not been addressed. Traditionally, in logic synthesis, delay optimization techniques have heavily relied on gate sizing algorithms which vary drive strengths of gates to optimize circuit delay. Since the delay in CMOS logic circuits not only depends on the drive strengths of each stage, but also on the width ratio of the P-channel and N-channel devices (P/N width ratio), it is crucial to make available a simple method to provide optimal P/N width ratios for inverters incorporating multiple-gate transistors.
Referring back to FIGS. 1A and 1B, a double-gate MOSFET structure 10 is shown. FIG. 1A shows the cross-sectional view of the double-gate MOSFET 10 through its channel region where the semiconductor fin 20 forms the channel and a gate electrode 16 straddles over the semiconductor fin 20, forming two gates 26,28, one on each of the two sidewalls 36,38 of the semiconductor fin 20. The plane view of the double-gate MOSFET structure 10 is shown in FIG. 1B. The width of a double-gate MOSFET formed using a single semiconductor fin is two times the fin height h, that is, the width of the double-gate MOSFET is equal to 2h. Varying the fin width for the double-gate MOSFET has no effect on the device width. Multiple device widths may be achieved on the same substrate by placing multiple fins in parallel. FIG. 2A shows the cross-sectional view of two double-gate MOSFETs connected in parallel. The width of the resulting parallel connection of two double-gate MOSFETs 4h. 
FIG. 4A shows the cross-sectional view of a triple-gate transistor 50 through the channel region. The triple-gate transistor is similar to the double-gate transistor except for the absence of the mask on the top surface 52 of the semiconductor fin 20. The gate dielectric 58 wraps around the semiconductor fin 20 on three sides, and the gate electrode 48 straddles over the fin 20. The gate electrode 48 forms three gates: a gate 62 on the top surface 52 of the semiconductor fin 20 and a gate 64,66 on each of the two sidewalls 54,56 of the fin. The device width of the triple-gate MOSFET 50 is given by the sum of the fin width and twice the fin height, e.g. (2h+w). Note that in this device structure, a variation of the fin width w changes the device width. The value of fin width w may be varied by altering the layout as schematically illustrated in FIG. 4C. A three-dimensional perspective of the triple-gate MOSFET 50 is shown in FIG. 5A.
Triple-gate transistors may have a recessed insulator layer for improved gate control, as illustrated in FIG. 4B. Such a structure is also known as the Omega field-effect transistor (FET), or simply omega-FET, since the gate electrode has an omega-shape in its cross-sectional view. The encroachment of the gate electrode under the semiconductor fin or body forms an omega-shaped gate structure. It closely resembles the gate-all-around (GAA) transistors for excellent scalability, and uses a manufacturable process similar to that of the double-gate or triple-gate transistor. The omega-FET has a top gate 62, two sidewall gates 64,66, and special gate extensions or encroachments 68 under the semiconductor body. The omega-FET is therefore a field effect transistor with a gate that almost wraps around the body. In fact, the longer the gate extension, e.g. the greater the extent of the encroachment E, the more the structure approaches or resembles the gate-all-around structure. A three-dimensional perspective of the triple-gate transistor 50 with recessed insulator, or omega-FET, is schematically illustrated in FIG. 5B. The encroachment of the gate electrode 48 under the silicon body helps to shield the channel from electric field lines from the drain and improves gate-to-channel controllability, thus alleviating the drain-induced barrier lowering effect and improving short-channel performance. The encroachment 68 of the gate electrode under the silicon body relies on an undercut 88 of the insulator layer 18 on the substrate 14, thus forming an undercut 88 in the substrate 14 at the base of the silicon body. It should be noted that the device width of the omega-FET is given by the sum of the fin width w, twice the fin height h, and twice the encroachment E. Therefore, the device width is given by (w+2h+2E). A variation of the fin width for the omega-FET changes the device width.
The plane view showing the triple-gate transistor of FIG. 4A, or the omega-FET of FIG. 4B, is shown in FIG. 4C. Both cross-sections in FIGS. 4A and 4B are drawn along line A–A′.
It is therefore an object of the present invention to provide an inverter formed of multiple-gate metal oxide semiconductor field effect transistors.
It is another object of the present invention to provide a method for fabricating an inverter by multiple-gate metal oxide semiconductor field effect transistors.